Alif Semiconductor /AE722F80F55D5AS_CM55_HE_View /DSI /DSI_PHY_TMR_LPCLK_CFG

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Interpret as DSI_PHY_TMR_LPCLK_CFG

31282724232019161512118743000000000000000000000000000000000000000000PHY_CLKLP2HS_TIME0PHY_CLKHS2LP_TIME

Description

Clock Lane Timer Configuration Register

Fields

PHY_CLKLP2HS_TIME

This field configures the maximum time that the D-PHY clock lane takes to go from low-power to high-speed transmission measured in LANEBYTECLK cycles.

PHY_CLKHS2LP_TIME

This field configures the maximum time that the D-PHY clock lane takes to go from high-speed to low-power transmission measured in LANEBYTECLK cycles.

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